1. Field of the Invention
This invention relates to the partitioning of memory, and more particularly to the partitioning of memory into buffer pairs for use in transmit and receive protocols.
2. Description of Related Art
A computer system often contains a memory located between communicating components of the system. This memory compensates for differences in transmitting, receiving, or processing speeds of the components. The memory stores data so that the slower component is not overwhelmed, and frees the faster component for other tasks. In addition, the memory can act as a switchboard, routing data to the proper receiving component. Each sending component can place a message into the memory, and then a control circuit for the memory could read an address header in the message to determine which component receives the message.
The memory is often partitioned into blocks, or buffers, to facilitate data transfer between the components. A primary advantage to partitioning is that each buffer contains only one (or a portion of one) message, and this increases the speed of the memory control program. In addition, in many communication protocols, each message has a maximum length, sometimes called a frame size. By making the size of the buffer equal to the frame size, each message will occupy only one buffer, and further increases in speed are possible.
Traditional methods of partitioning memory into buffers divide the block into a number of buffers of equal size (called the blocking factor). Both the number of buffers, and the size of buffers, are typically a power of two. For example, a 32Kbyte memory block could be partitioned as two buffers with a blocking factor of 16Kbytes, four buffers with a blocking factor of 8Kbytes, eight buffers with a blocking factor of 4Kbytes, and so on. Each buffer is then used to temporarily hold a unit of data for transfer between components of the computer system.
A memory utilization problem occurs in data transfer if the typical size of a transferred block of data is just slightly larger than the blocking factor. For example, if each buffer is 2048 bytes, and a typical transfer is 2072 bytes, then the additional 24 bytes must be stored in a second buffer. Alternately, the blocking factor could be increased by a factor of two to 4096 bytes. In both cases, a significant portion of available memory is wasted. This inefficient memory utilization problem is common in data transfer systems due to the addition of control information to the data. As shown in FIGS. 1 and 2, data is usually transferred between components of a computer system 10 in packets 30. The computer system 10 typically includes nodes 12, such as computers, printers, and servers, linked by local area networks 15. Local area networks (LANs) 15 may themselves be linked by a wide area network (WAN) 17. In addition, each node 12 may be connected to devices 22, such as disk drives or other peripheral components, through a communication link 25. The communication link 25 may be a familiar interface such as a SCSI or a peripheral component interconnect (PCI). Each device 22 is connected to the communications link 25 by a bus interface unit (BIU) 27.
A typical packet 30 contains a data portion 32, a header 34, and a trailer 36. The header 34 identifies the source and destination of the data 32 and may contain other control information. The endpoints of a particular data transfer (i.e., the source and destination) are likely to use an efficient blocking factor to ensure efficient memory storage. Each time a packet 30 moves in a computer system 10, additional information may be added to the header 34.
There are three problems when a data packet 30 is stored in a buffer between the endpoints of a data transfer. First, because the header 34 has been added to the data 32, the packet as a whole no longer has an efficient overall blocking factor. Therefore, the memory utilization difficulty mentioned above is more likely to occur. Second, some intervening control information in the header 34 must be skipped when transferring multiple blocks of packet data out of the buffer. This introduces inefficiencies, such as when a direct memory access (DMA) state machine needs to be reinitialized at each new buffer transfer. Whether the data packet 30 is moving between devices 22 connected to the same link 25, or between hosts connected by WAN 17, inefficient use of buffers may occur.
Memory blocks have been divided into pairs of buffers holding related information for data transfer purposes. It is desirable to refer to a buffer pair using a single address to ensure a link between the buffers and for ease of processing. One traditional method of addressing a buffer pair is to use a lookup table, but this requires software intervention. Another method is to use a sequential access rule in which buffer N holds control information and buffer N+1 holds data, but this requires the two buffers to be the same size. Another method is to concatenate the control information and data in a single buffer, with the data starting at a known offset from the control information, but this requires an inefficient oversized buffer. Another problem with some of the above methods is that the addition of a single memory component requires reconfiguring the addressing scheme.
Hardware-based mechanisms for linking buffer pairs require physically separate memories, because the simplest way to allocate scalable addressing for split buffers is to have an address gap between the two buffer sets in the minimum configuration.
In view of the foregoing, it is an object of the invention to provide a simple method of partitioning a memory which supports a split buffer pair with a large buffer to hold data and at least one associated small buffer to hold control information.
It is another object of the invention to address such a split buffer pair with a single address.
It is yet another object of the invention to provide a split buffer model in which the memory is scalable, with each memory block having the same partitioning as the first block, and in which the total memory may be easily increased by the addition of a single memory component.
It is still another object of the invention to provide a first-in-first-out device to manage the available split buffers.
The present invention meets these needs.